1. Technical Field
The present invention relates to a circuit and method for detecting the phase of a received signal and removing interference from the received signal in a demodulation circuit of a digital communications system. More particularly, the invention relates to a circuit for removing interference from the received signal by using an adaptive time domain equalizer.
2. Related Art
Typically, a demodulation circuit in a digital communications system includes a signal processing unit, two mixers, two AID converters and a phase restoring unit. A local oscillator is connected directly to one of the mixers and, through a phase shift unit, to the other of the mixers. A symbol clock restoring unit is connected to each of the A/D converters.
Such a demodulation circuit in a digital communications system has been burdened by disadvantages in the past. As a result, there has been a need to develop a demodulation circuit for a digital communications system, wherein the demodulation circuit further includes an equalizer connected between each of the A/D converters and the phase restoring unit. However, there has been a further problem in that the construction of a logic circuit for restoring phase to the signal being processed is complicated. A further problem resides in the fact that the operational range of the A/D converters cannot be sufficiently utilized. This causes the input to the A/D converters to be reduced, and this results in a quantization error.
Therefore, there is a need to develop a circuit and method for removing interference by restoring phase, and there is a further need to develop such a circuit and method for removing interference so as to reduce quantization error generated by the A/D converters. There is also a need to develop a circuit and method for removing interference of a common signal and an orthogonal a phase signal.
The following patents are considered to be representative of the prior art relative to the present invention, but are burdened by the disadvantage discussed above: U.S. Pat. No. 5,524,124 to Koening, entitled Multiple-Filter Equalizer For Structured Digitally Modulated Signals, U.S. Pat. No. 5,519,727 to Okanoue et al., entitled Adaptive Equalizer, U.S. Pat. No. 5,502,507 to Kim, entitled Equalization Apparatus With Fast Coefficient Updating Operation, U.S. Pat. No. 5,418,816 to Yamamoto, entitled Automatic Equalizer, U.S. Pat. No. 5,394,110 to Mizoguchi, entitled Demodulation System Having Adaptive Matched Filter And Decision Feedback Equalizer, U.S. Pat. No. 5,363,411 to Furuya et al., entitled Low Power Consumption Receiver With Adaptive Equalizer, U.S. Pat. No. 5,251,233 to Labedz et al., entitled Apparatus And Method For Equalizing A Corrupted Signal In A Receiver, U.S. Pat. No. 5,157,690 to Buttle, entitled Adaptive Convergent Decision Feedback Equalizer, U.S. Pat. No. 4,730,343 to Kanemasa et al., entitled Decision Feedback Equalizer With A Pattern Detector, U.S. Pat. No. 4,703,282 to Yoshida, entitled Digital Demodulation System, U.S. Pat. No. 4,468,786 to Davis, entitled Nonlinear Equalizer For Correcting Intersymbol Interference In A Digital Data Transmission System, U.S. Pat. No. 4,320,523 to Horikawa et al., entitled Digital Signal Reception System, and U.S. Pat. No. 4,021,738 to Gitlin et al., entitled Adaptive Equalizer With Fast Convergence Properties.